Key Requirements of a Multi-stage FPGA Routing Fabric Adoptable to a Prevailing FPGA Architecture

  • We have 10+ years of customer interaction, implementation, and validation in various FPGA Architectures.
  • Since our business model is IP licensing, we understand each of our customer’s specific needs and of course Konda Fabric is designed/delivered to meet the following customer needs:
  • Logic block or Logic Module:
    • Fabrics need to be adoptable to:
      • Coarse-grain Cluster of LUT based Logic blocks
        • May need to be replicable for each slice (sub-cluster)
      • Fine-grain LUT based logic blocks
    • Fabrics need to be adoptable to any size of inlet links or outlet links
      • Number of inlet links may or may not be equal to outlet links
      • Number of inlet links and outlet links may be odd or even
      • Number of inlet links and outlet links may or may not be perfect power of d where d >= 2
  • Multiplexers:
    • Same number & type of Muxes for each logic block.
    • Fabric should be adoptable for any size of Muxes.
  • Wiring/Tracks:
    • External wires need to be either horizontal or vertical (Cannot be L shaped or H shaped wires)
    • Same internal wiring for each logic block
    • Same external wiring for each logic block
    • External wires need to be of any arbitrary size
    • Adoptable for segmented wiring.
    • Adoptable to single drop or multi-drop wires
  • Physical Layout Size:
    • Physical wiring layout should be congestion free
    • Physical layout should not have any holes
  • Locality exploitation:
    • Nearer neighbor logic blocks need to have shorter paths
  •  Performance
    • Only one mux delay for cascaded long wires in each Cluster.
  • Routing:
    • All the routing resources need to be available for routing regardless of the size of the placed benchmark
  • Placement with/without Hierarchy:
    • Regardless of where in the FPGA grid the emulated circuit is placed, similar routing resources and metrics achievable.
  • FPGA Scalability:
    • Fabric should be adoptable to any arbitrary size of rows and columns.
  • Fabric Optimization:
    • Multiplexers need to be depopulatable.
    • Individual wires need to be addable or removable.
  • Speed of routing:
    • Fabric should route benchmarks fast in parity with prevailing 2D Mesh networks

More details to be furnished in direct interaction.