Konda FPGA Routing Fabric
Konda FPGA Routing Fabric is an FPGA-friendly Network derived from 2D Multi-stage Network after performing a series of transformations, techniques and optimizations. A few (complete list is not provided here) of those transformations, techniques and optimizations are described below. Also Konda FPGA Routing Network is a network comprising any subset of the properties described below (So Konda FPGA Routing Fabric has many variety of structures and properties):
- Based on 2D Multi-stage network with N*logN crosspoint complexity
- 2D BFT Network
- 2D BFT Pyramid Network
- 2D Benes Network
- 2D Benes Pyramid Network
- 2D Multi-stage Network etc.
- We use any of the above terms interchangeably to refer to all of them including on this web site.
- Isomorphic transformations applied
- Logic block or Logic Module:
- Fabric is adoptable to:
- Coarse-grain Cluster of LUT based Logic blocks
- also replicable for each slice (sub-cluster)
- Fine-grain LUT based logic blocks
- Coarse-grain Cluster of LUT based Logic blocks
- Fabric is adoptable to any size of inlet links or outlet links:
- Number of inlet links may or may not be equal to outlet links
- Number of inlet links and outlet links may be even or odd
- Number of inlet links and outlet links may or may not be perfect power of d where d >= 2
- Fabric is adoptable to:
- Multiplexers:
- Same number & type of Muxes for each logic block.
- If needed different number and different type of Muxes for each block as well.
- Fabric is adoptable for any size of Muxes.
- Muxes are designed so that 180 degree U turn paths are not provisioned.
- Same number & type of Muxes for each logic block.
- Wiring/Tracks:
- External wires are either horizontal or vertical
- Same internal wiring for each logic block
- Same external wiring for each logic block
- External wires can be any arbitrary size
- Adoptable for segmented wiring.
- Adoptable to single drop or multi-drop wires
- May or may not have alternative vertical and horizontal wiring
- Physical Layout Size:
- Physical wiring layout is congestion free
- Physical layout does not have any holes
- Locality exploitation:
- Nearest neighbor logic blocks have shorter paths
- Performance:
- Only one mux delay for cascaded long wires in each Cluster.
- Routing:
- All the routing resources are available for routing regardless of the size of the placed benchmark.
- If needed routing resources are provided based on hierarchy
- All the routing resources are available for routing regardless of the size of the placed benchmark.
- Placement with/without Hierarchy:
- Regardless of where in the FPGA grid the emulated circuit is placed, similar routing resources and metrics achievable.
- If desired different metrics are achievable for different locations of placement.
- Regardless of where in the FPGA grid the emulated circuit is placed, similar routing resources and metrics achievable.
- FPGA Scalability:
- Fabric grows to any arbitrary size of row-by-row or column-by-column.
- Fabric Optimization:
- Switches or Multiplexers are depopulatable.
- Individual wires are addable or removable.
- Two sided Fabric architecture with reverse U-turns
- Small number of stages
- Flexible to connect inlet/outlet links or any link in the middle of rings.
- Speed of routing:
- Fabric routes benchmarks faster in parity with prevailing 2D Mesh network.
- Significant advantages over the prevailing Routing Fabrics:
- ~3X die area improvements as well as significant improvements in all other dimensions such as power, performance and wire (metal layer) reduction.