Is 2D Multi-Stage Network Productizable as an FPGA Fabric as is?

Even though 2D BFT network solved the main hurdle of all external wires being either horizontal and vertical wires, if it is implemented as an FPGA Fabric as is, it will be very inefficient. Clearly a 2D Multi-stage network is implementable as an FPGA Fabric as is. The following are the properties of 2D BFT Network:

  • Fully connected Network:
    • 2D BFT Network is a fully connected network which is an over-kill as an FPGA Fabric.
  • Logic block or Logic Module:
    • 2D BFT networks are not inherently defined for:
      • Coarse-grain cluster of LUT based Logic blocks
        • Also not replicable for each slice (or sub-cluster)
      • Fine-grain LUT based logic blocks
    • 2D BFT networks are not inherently defined for any size of inlet links or outlet links
      • Number of inlet links need to be equal to outlet links.
      • Number of inlet links and outlet links may need to be even.
      • Number of inlet links and outlet links need to be perfect power of d where d >= 2.
      • Inlet and outlet links are connected only from one side.
  • Multiplexers:
    • 2D BFT networks are not inherently defined to have same number Muxes for each logic block
    • 2D BFT networks are inherently defined for any size of Muxes
  • Wiring/Tracks:
    • 2D BFT networks are inherently defined for external wires need to be either horizontal or vertical but they are alternative horizontal and vertical wires
    • No concept of internal wiring for each logic block
    • Not the same external wiring for each logic block
    • External wires are of size d^n.
    • 2D BFT networks are inherently defined with segmented wiring.
    • 2D BFT networks are not inherently defined with multi-drop wires
  • Physical Layout size:
    • Physical wiring layout gets congested as the stage height increases
    • Physical layout have holes at Root stage.
  • Locality exploitation:
    • 2D BFT networks inherently do not exhibit Nearest neighbor locality of logic blocks.
  • Performance:
    • Cascaded long wires in each block incur more than one Mux delay
  • Routing:
    • All the routing resources are not available for routing regardless of the size of placed benchmark.
    • Routing resources are available hierarchically only.
  • Placement:
    • Regardless of where in the FPGA grid the emulated circuit is placed, similar routing resources and metrics are not achievable.
  • FPGA Scalability:
    • 2D BFT networks are not inherently adoptable to any arbitrary size of rows and columns.
    • They are defined to be double the size for scalability.
  • Fabric Optimization:
    • 2D BFT networks are inherently defined with depopulatable multiplexers.
    • 2D BFT networks are inherently defined with addable and removable Individual wires.
    • Wastes resources with only one U-turn in each path
    • Wastes resources with Inherent 180 degree turns
  • Speed of routing:
    • 2D BFT networks are not inherently defined to route benchmarks faster in parity with prevailing 2D Mesh networks