Konda Technologies Granted Patent Portfolio
Latest Update: USPTO awarded us five New Patents: US 11,777,872; US 11,405,331; US 11,405,332; US 11,451,490 & US 11,509,605 in 2022-23
- Automatic Multi-stage Fabric Generation for FPGAs
- Priority date: September 7, 2011
- US Date Filed: November 1, 2019
- US Patent Number: US 10,965,618
- US Date of Patent: March 30, 2021
- VLSI Layouts of Fully Connected Generalized and Pyramid Networks with Locality Exploitation
- Priority date: October 16, 2009
- US Date Filed: November 1, 2019
- US Patent Number: US 10,977,413
- US Date of Patent: April 13, 2021
- Fast Scheduling and Optimization of Multi-stage Hierarchical Networks
- Priority date: July 15, 2013
- US Date Filed: September 6, 2019
- US Published on March 5, 2020: US 20200076744 A1
- US Patent Number: US 10,979,366
- US Date of Patent: April 27, 2021
- Optimization of Multi-stage Hierarchical Networks for Practical Routing Applications
- Priority date: September 7, 2011
- US Date Filed: November 1, 2019
- US Patent Number: US 10,992,597
- US Date of Patent: April 13, 2021
- VLSI Layouts of Fully Connected Generalized Networks
- Priority date: May 25, 2007
- PCT Date Filed: May 22, 2008
- PCT Published on December 4, 2008: WO 2008147928 A1
- US Date Filed: November 27, 2018
- US Patent Application Number: 16/202,067
- Automatic Multi-stage Fabric Generation for FPGAs
- Priority date: September 7, 2011
- US Date Filed: January 1, 2018
- US Published on May 10, 2018: US 2018013636 A1
- US Patent Number: US 10,536,399
- US Date of Patent: January 14, 2020
- VLSI Layouts of Fully Connected Generalized and Pyramid Networks with Locality Exploitation
- Priority date: October 16, 2009
- US Date Filed: July 8, 2018
- US Published on January 31, 2019: US 20190036844 A1
- US Patent Number: US 10,554,583
- US Date of Patent: February 4, 2020
- Optimization of Multi-stage Hierarchical Networks for Practical Routing Applications
- Priority date: September 7, 2011
- US Date Filed: May 20, 2018
- US Patent Number: US 10,574,594
- US Date of Patent: February 25, 2020
- Fast Scheduling and Optimization of Multi-stage Hierarchical Networks
- Priority date: July 15, 2013
- US Date Filed: January 31, 2018
- US Published on July 26, 2018: US 2018021899A1
- US Patent Number: US 10,412,025
- US Date of Patent: September 10, 2019
- VLSI Layouts of Fully Connected Generalized and Pyramid Networks with Locality Exploitation
- Priority date: October 16, 2009
- US Date Filed: November 15, 2016
- US Published on March 9, 2017: US 20170070449 A1
- US Patent Number: US 10,050,904
- US Date of Patent: August 14, 2018
- Optimization of Multi-stage Hierarchical Networks for Practical Routing Applications
- Priority date: September 7, 2011
- US Date Filed: April 28, 2016
- US Published on September 8, 2016: US 20160261525 A1
- US Patent Number: US 10,003,553
- US Date of Patent: June 19, 2018
- Fast Scheduling and Optimization of Multi-stage Hierarchical Networks
- Priority date: July 15, 2013
- US Date Filed: October 22, 2016
- US Published on March 9, 2017: US 20150049768A1
- US Patent Number: US 9,929,977
- US Date of Patent: March 27, 2018
- VLSI Layouts of Fully Connected Generalized and Pyramid Networks with Locality Exploitation
- Priority date: October 16, 2009
- US Date Filed: October 24, 2014
- US Published on February 12, 2015: US 20150046895 A1
- US Patent Number: US 9,529,958
- US Date of Patent: December 27, 2016
- Fast Scheduling and Optimization of Multi-stage Hierarchical Networks
- Priority date: July 15, 2013
- US Date Filed: July 11, 2014
- US Published on February 19, 2015: US 20150049768A1
- US Patent Number: US 9,509,634
- US Date of Patent: November 29, 2016
- Optimization of Multi-stage Hierarchical Networks for Practical Routing Applications
- Priority date: September 7, 2011
- PCT Date Filed: September 6, 2012
- PCT Published on March 14, 2013: WO 2013036544 A1
- US Date Filed: March 6, 2014
- US Published on October 23, 2014: US 20140313930 A1
- US Patent Number: US 9,374,322
- US Date of Patent: June 21, 2016
- VLSI Layouts of Fully Connected Generalized and Pyramid Networks with Locality Exploitation
- Priority date: October 16, 2009
- PCT Date Filed: October 16, 2010
- PCT Published on April 21, 2011: WO 2011047368 A2
- US Date Filed: April 16, 2012
- US Published on October 25, 2012: US 2012/0269190 A1
- US Patent Number: US 8,898,611
- US Date of Patent: November 25, 2014
- VLSI Layouts of Fully Connected Generalized Networks
- Priority date: May 25, 2007
- PCT Date Filed: May 22, 2008
- PCT Published on December 4, 2008: WO 2008147928 A1
- US Date Filed: November 22, 2009
- US Published on February 17, 2011: US 2011/0037498 A1
- US Patent Number: US 8,269,523
- Date of Patent: September 18, 2012
- Fully Connected Generalized Multi-link Multi-stage Networks
- Priority date: May 25, 2007
- PCT Date Filed: May 22, 2008
- PCT Published on December 4, 2008: WO 2008147927 A1
- US Date Filed: November 22, 2009
- US Published on February 24, 2011: US 2011/0044329 A1
- US Patent Number: US 8,363,649
- US Date of Patent: January 29, 2013
- Fully Connected Generalized Butterfly Fat Tree Networks
- Priority date: May 25, 2007
- PCT Date Filed: May 22, 2008
- PCT Published on December 4, 2008: WO 2008147926 A1
- US Date Filed: November 22, 2009
- US Published on July 8, 2010: US 2010/0172349 A1
- US Patent Number: US 8,170,040
- US Date of Patent: May 1, 2012
- Fully Connected Generalized Multi-stage Networks
- Priority date: March 6, 2007
- PCT Date Filed: March 6, 2008
- PCT Published on December 9, 2008: WO 2008109756 A1
- US Date Filed: September 6, 2009
- US Published on June 3, 2010: US 2010/0135286 A1
- US Patent Number: US 8,270,400
- US Date of Patent: September 18, 2012
- More pending